NewsSecurity Vulnerabilities

NetCAT CPU Vulnerability [CVE-2019-11184]

CVE number – CVE-2019-11184

A race condition in specific microprocessors using Intel (R) DDIO cache allocation and RDMA may allow an authenticated user to potentially enable partial information disclosure via adjacent access.

NetCAT stands for Network Cache ATtack. “netcat” is also a famous utility that hackers and system administrators use to send information over the network. cat is the UNIX tool to read the contents a file, netcat is supposed to do the same over the network. NetCAT is a pun on being able to read data from the network without cooperation from the other machine on the network.

Affected Platforms

  • Intel Xeon E5, E7 and SP families that support DDIO and RDMA

Recommendations

DDIO is enabled transparently by default in all Intel server-grade processors since 2012 (Intel Xeon E5, E7 and SP families).

Partial information potentially disclosed through exploitation of this vulnerability could be utilized to enhance unrelated attack methods.  For published exploits that Intel is aware of, Intel recommends users follow existing best practices including:

Where DDIO & RDMA are enabled, limit direct access from untrusted networks. If DDIO is available/enabled on your platform, you are affected by the vulnerability. If RDMA is also enabled, the vulnerability immediately exposes your server to practical side-channel attacks over the network.

You can disable DDIO by adjusting the Integrated I/O (IIO) configuration registers. There are two possibilities, changing it globally (Disable_All_Allocating_Flows bit) or per root PCIe port (NoSnoopOpWrEn and Use_Allocating_Flow_Wr bit). We successfully mitigated NetCAT by setting these bits on our Intel Xeon E5 cluster. For the Intel Xeon SP families, the offsets of these bits are not (yet) publicly documented.

Security Best Practices For Side Channel Resistance:

https://software.intel.com/security-software-guidance/insights/security-best-practices-side-channel-resistance

Guidelines For Mitigating Timing Side Channels Against Cryptographic Implementations:

https://software.intel.com/security-software-guidance/insights/guidelines-mitigating-timing-side-channels-against-cryptographic-implementations

Intel would like to thank Michael Kurth, Ben Gras, Dennis Andriesse, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi from VU Amsterdam for reporting this issue.

Jason Davies

I am one of the editors here at www.systemtek.co.uk I am a UK based technology professional, with an interest in computer security and telecoms.

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